HiBRID-SoC: A system-on-chip architecture with two multimedia DSPs and a RISC core

被引：4

作者：

Friebe, L ^{[1
]}

Stolberg, HJ ^{[1
]}

Berekovic, M ^{[1
]}

Moch, S ^{[1
]}

Kulaczewski, MB ^{[1
]}

Dehnhardt, A ^{[1
]}

Pirsch, P ^{[1
]}

机构：

[1] Leibniz Univ Hannover, Inst Mikroelekt Syst, D-30167 Hannover, Germany

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/SOC.2003.1241468

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The HiBRID-SoC integrates three fully programmable processor cores, each optimized towards a particular class of algorithms: the HiPAR-DSP for DSP oriented functions, the Macroblock Processor for block oriented algorithms, and the Stream Processor for bitstream processing. Dedicated interface units for SDRAM, serial Flash, and host system access are connected via a 64-bit AMBA AHB system bus with the processor cores. Dual-port memories between the processor cores facilitate fast data and control information exchange between the cores. The HiBRID-SoC is fabricated in a 0.18 mum 6LM standard-cell technology, occupies about 82 mm(2), and operates at 160 MHz.

引用

页码：85 / 88

页数：4

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