Accelerating a MPEG-4 video decoder through custom software/hardware co-design

被引:0
|
作者
Diaz, Jorge L. [1 ]
Barreto, Dacil [1 ]
Garcia, Luz [1 ]
Marrero, Gustavo [1 ]
Carballo, Pedro P. [1 ]
Nunez, Antonio [1 ]
机构
[1] Univ Las Palmas Gran Canaria, IUMA, Inst Appl Microelect, Las Palmas Gran Canaria 35017, Spain
来源
关键词
MPEG-4 video decoder; CASSE; motion compensation; IDCT; software/hardware co-design; hardware coprocessors; verification; integration; FPGA;
D O I
10.1117/12.722068
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper we present a novel methodology to accelerate an MPEG-4 video decoder using software/hardware co-design for wireless DAB/DMB networks. Software support includes the services provided by the embedded kernel mu C/OS-II, and the application tasks mapped to software. Hardware support includes several custom co-processors and a communication architecture with bridges to the main system bus and with a dual port SRAM. Synchronization among tasks is achieved at two levels, by a hardware protocol and by kernel level scheduling services. Our reference application is an MPEG-4 video decoder composed of several software functions and written using a special C++ library named CASSE. Profiling and space exploration techniques were used previously over the Advanced Simple Profile (ASP) MPEG-4 decoder to determinate the best HW/SW partition developed here. This research is part of the ARTEMI project and its main goal is the establishment of methodologies for the design of real-time complex digital systems using Programmable Logic Devices with embedded microprocessors as target technology and the design of multimedia systems for broadcasting networks as reference application.
引用
收藏
页数:8
相关论文
共 50 条
  • [21] Accelerating Database Workloads by Software-Hardware-System Co-design
    Bordawekar, Rajesh R.
    Sadoghi, Mohammad
    [J]. 2016 32ND IEEE INTERNATIONAL CONFERENCE ON DATA ENGINEERING (ICDE), 2016, : 1428 - 1431
  • [22] Video processor design using hardware and software co-design strategy
    Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
    [J]. Zhejiang Daxue Xuebao (Gongxue Ban), 2006, 7 (1117-1122):
  • [23] Software-Hardware Co-design for Video Coding Acceleration
    Niu, Xinwei
    Galarza, Luis
    Gao, Ying
    Fan, Jeffrey
    [J]. 2012 44TH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY (SSST), 2012, : 57 - 60
  • [24] Hardware/software co-design
    De Micheli, Giovanni
    Gupta, Rajesh K.
    [J]. Proceedings of the IEEE, 1997, 85 (03): : 349 - 365
  • [25] Hardware/software co-design
    Edwards, M
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 1996, 20 (03) : 139 - 140
  • [26] On the design flow of a hardware/software platform for MPEG-4 part 9 reference hardware model
    Mohamed, T
    Sayed, M
    Badawy, W
    [J]. ICEEC'04: 2004 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING, PROCEEDINGS, 2004, : 399 - 402
  • [27] Parallel algorithm implementation of MPEG-4 video decoder on DSP
    Li, DM
    Li, ZH
    [J]. NEURAL NETWORK AND DISTRIBUTED PROCESSING, 2001, 4555 : 148 - 153
  • [28] A real-time realization of MPEG-4 video decoder
    Chau, LP
    Ling, N
    Hovden, G
    Lan, H
    Ng, HC
    Lim, KP
    [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI, 1999, : 222 - 225
  • [29] Cost-efficient C-level design of an MPEG-4 video decoder
    Denolf, K
    Vos, P
    Bormans, J
    Bolsens, I
    [J]. INTEGRATED CIRCUIT DESIGN, PROCEEDINGS: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2000, 1918 : 233 - 242
  • [30] Accelerating an FPGA-Based SAT Solver by Software and Hardware Co-design
    Ma, Kefan
    Xiao, Liquan
    Zhang, Jianmin
    Li, Tiejun
    [J]. CHINESE JOURNAL OF ELECTRONICS, 2019, 28 (05) : 953 - 961