A novel receiver in high-speed serial data link

被引：0
|
作者：
Li, HL [1 ]
Mao, C [1 ]
Xiong, J [1 ]
Men, CY [1 ]
He, LN [1 ]
Yan, XL [1 ]
机构：
[1] Zhejiang Univ, Inst VLSI Design, Hangzhou 310027, Peoples R China
来源：
2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2003年
关键词：
receiver; data sampling; high-speed; rising and falling time;
D O I：
10.1109/ICASIC.2003.1277626
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this work, we proposed a novel receiver with three stages circuits. i.e.. voltage-conversion, data-sampling and data-holding. The simulation results revealed that the receiver designed in this method reduced the rising and falling time of the input data from 700 ps to 140 ps in data-sampling circuit. It suggests that the accuracy and resolution for sampled data were improved.
引用
收藏
页码：623 / 626
页数：4
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