A bottom-up approach for System-On-Chip reliability

被引：19
|
作者：
Huard, V. [1 ]
Ruiz, N. [1 ]
Cacho, F. [1 ]
Pion, E. [1 ]
机构：
[1] STMicroelectronics, Alliance Crolles2, F-38926 Crolles, France
来源：
MICROELECTRONICS RELIABILITY | 2011年 / 51卷 / 9-11期
关键词：
D O I：
10.1016/j.microrel.2011.07.086
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy. (C) 2011 Elsevier Ltd. All rights reserved.
引用
收藏
页码：1425 / 1439
页数：15
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