An Optimized VLSI Implementation of an IEEE 802.11n/ac/ax LDPC Decoder

This paper proposes optimization techniques for multi-Gbps low-power VLSI implementation of IEEE 802.11n/ac/ax (WiFi) LDPC decoders. The IEEE 802.11n/ac/ax standard features Quasi-Cyclic LDPC (QC-LDPC) codes with modular decoder structure composed of arrays of memory blocks, barrel shifter networks, adders, and check-node units (CNUs). To achieve multi-Gbps throughput performance and high energy-efficiency while maintaining a small decoder footprint, careful implementation of these modules along with effective fixed-point analysis is required. This paper proposes techniques for optimized implementation and proper bit-width selection of these modules. These techniques are then employed to design a fully-pipelined IEEE 802.11n/ac/ax standard compliant LDPC decoder. The design is synthesized in a 40 nm standard CMOS process. The synthesized decoder occupies an area of 0.71 mm(2), runs at a frequency of 562 MHz, attains a peak throughput of 11.4 Gbps, and achieves an energy-efficiency of 12.5 pJ/bit. The presented decoder outperforms the best reported decoders in the literature in terms of throughput/area and energy-efficiency, for IEEE 802.11n/ac/ax LDPC codes.