Hierarchical statistical inference model for specification based testing of analog circuits

被引：8
|
作者：
Yoon, H [1 ]
Variyam, P [1 ]
Chatterjee, A [1 ]
Nagi, N [1 ]
机构：
[1] Georgia Inst Technol, Sch ECE, Atlanta, GA 30332 USA
来源：
16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1998年
关键词：
D O I：
10.1109/VTEST.1998.670862
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we propose a framework for analyzing the effects of circuit parameter variations on high level system specifications in a hierarchical manner. The effects of parameter variations in one level of design hierarchy on those of the next are mapped through linear and piecewise linear sensitivity functions. The models allow computation of the statistical distributions of the circuit parameters and their correlations. This data is used to determine the critical circuit specifications that must be measured and those that may be eliminated from the testing process.
引用
收藏
页码：145 / 150
页数：6
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