Influences of the Source and Drain Resistance of the MOSFETs on the Single Event Upset Hardness of SRAM cells

被引：0
|
作者：
Zheng, Zhongshan [1 ,2 ]
Li, Zhentao [1 ]
Li, Bo [1 ,2 ]
Luo, Jiajun [1 ,2 ]
Han, Zhengsheng [1 ,2 ,3 ]
机构：
[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China
[2] Chinese Acad Sci, Key Lab Silicon Device Technol, Beijing 100029, Peoples R China
[3] Univ Chinese Acad Sci, Beijing 100049, Peoples R China
来源：
2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2019年
关键词：
D O I：
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The influences of the source and drain resistance of both the nMOSFETs and pMOSFETs on the single event response of SRAM cells have been investigated by the SPICE simulations. The results show that the source and drain resistance of the nMOSFETs can increase the single event upset (SEU) hardness of a cell, whereas the source and drain resistance of the pMOSFETs result in a reduction in the SEU hardness, with the drain region of the OFF-state nMOSFET struck by particles. In addition, the SEU hardness also reveals a non-monotonic variation feature with increasing source and drain resistance.
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页数：3
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