Low-power VLSI architectures for OFDM transmitters based on PAPR reduction

被引：0
|
作者：
Giannopoulos, T [1 ]
Paliouras, V [1 ]
机构：
[1] Univ Patras, Dept Elect & Comp Engn, Patras 25600, Greece
来源：
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2005年 / 3728卷
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper introduces a quantitative approach to the reduction of system-level power dissipation reducing the Peak-to-Average Power Ratio (PAPR) in multicarrier systems. In particular introduces a VLSI implementation of Partial Transmit Sequences (PTS) approach. PTS is a distortionless Peak-to-Average Power Ratio (PAPR) reduction scheme suitable for Orthogonal Frequency Division Multiplexing (OFDM) which imposes low additional complexity to the overall system. We show that the application of this method reduces the power consumption of the complete digital-analog system by even 12.6%. Furthermore, this paper examines theoretically the relationship between the achieved PAPR reduction and the corresponding PA efficiency. Subsequently the achieved PAPR reduction and the corresponding power saving are evaluated via simulation.
引用
收藏
页码：177 / 186
页数：10
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