A 16nm 128Mb SRAM in High-κ Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMIN Applications

被引：0
|
作者：
Chen, Yen-Huei [1 ]
Chan, Wei-Min [1 ]
Wu, Wei-Cheng [1 ]
Liao, Hung-Jen [1 ]
Pan, Kuo-Hua [1 ]
Liaw, Jhon-Jhy [1 ]
Chung, Tang-Hsuan [1 ]
Li, Quincy [1 ]
Chang, George H. [1 ]
Lin, Chih-Yung [1 ]
Chiang, Mu-Chi [1 ]
Wu, Shien-Yang [1 ]
Natarajan, Sreedhar [1 ]
Chang, Jonathan [1 ]
机构：
[1] TSMC, Hsinchu, Taiwan
来源：
2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC) | 2014年 / 57卷
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：238 / +
页数：3
相关论文
共 25 条
  • [21] A 29.2 Mb/mm2 ultra high density SRAM macro using 7nm FinFET technology with dual-edge driven wordline/bitline and write/read-assist circuit
    Yokoyama, Yoshisato
    Tanaka, Miki
    Tanaka, Koji
    Morimoto, Masao
    Yabuuchi, Makoto
    Ishii, Yuichiro
    Tanaka, Shinji
    2020 IEEE SYMPOSIUM ON VLSI CIRCUITS, 2020,
  • [22] A 128-kb 25% Power Reduced 1T High Density ROM with 0.55 ns Access Time using Low Swing Bitline Edge Sensing in 16nm FinFET Technology
    Taneja, Sachin
    Verma, Vaibhav
    Dubey, Prashant
    2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2016,
  • [23] High-κ/Metal Gate Low Power Bulk Technology - Performance Evaluation of Standard CMOS Logic Circuits, Microprocessor Critical Path Replicas, and SRAM for 45nm and beyond
    Park, D. -G.
    Stein, K.
    Schruefer, K.
    Lee, Y.
    Han, J-P
    Li, W.
    Yin, H.
    Pacha, C.
    Kim, N.
    Ostermayr, M.
    Eller, M.
    Kim, S.
    Kim, K.
    Han, S.
    von Arnim, K.
    Moumen, N.
    Hatzistergos, M.
    Tang, T.
    Loesing, R.
    Chen, X.
    Jaeger, D.
    Zhuang, H.
    Chen, J.
    Yan, W.
    Kanarsky, T.
    Chowdhury, M.
    Haetty, Jens
    Schepis, D.
    Chudzik, M.
    Theon, V-Y
    Samavedam, S.
    Narayanan, V.
    Sherony, M.
    Lindsay, R.
    Steegen, A.
    Divakaruni, R.
    Khare, M.
    PROCEEDINGS OF TECHNICAL PROGRAM: 2009 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS, 2009, : 90 - 92
  • [24] A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology
    Lee, Inhak
    Jeong, Hanwool
    Baeck, Sangyeop
    Gupta, Siddharth
    Park, Changnam
    Seo, Dongwook
    Choi, Jaesung
    Kim, Jaeyoung
    Kim, Hoon
    Kang, Jungmyung
    Jang, Sunyung
    Moon, Daeyoung
    Han, Sangshin
    Kim, Taehyung
    Lim, Jaehyun
    Park, Younghwan
    Hwang, Hyejin
    Kang, Jeonseung
    Choi, Jaeseung
    Song, Taejoong
    2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2019, 62 : 392 - +
  • [25] A 32nm Logic Technology Featuring 2nd-Generation High-k plus Metal-Gate Transistors, Enhanced Channel Strain and 0.171μm2 SRAM Cell Size in a 291Mb Array
    Natarajan, S.
    Armstrong, M.
    Bost, M.
    Brain, R.
    Brazier, M.
    Chang, C-H
    Chikarmane, V.
    Childs, M.
    Deshpande, H.
    Dev, K.
    Ding, G.
    Ghani, T.
    Golonzka, O.
    Han, W.
    He, J.
    Heussner, R.
    James, R.
    Jin, I.
    Kenyon, C.
    Klopcic, S.
    Lee, S-H.
    Liu, M.
    Lodha, S.
    McFadden, B.
    Murthy, A.
    Neiberg, L.
    Neirynck, J.
    Packan, P.
    Pae, S.
    Parker, C.
    Pelto, C.
    Pipes, L.
    Sebastian, J.
    Seiple, J.
    Sell, B.
    Sivakumar, S.
    Song, B.
    Tone, K.
    Troeger, T.
    Weber, C.
    Yang, M.
    Yeoh, A.
    Zhang, K.
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, 2008, : 941 - 943
123