A 7.9-14.3GHz-243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS

被引：0
|
作者：
Wang, Yizhuo [1 ]
Zou, Tenghao [1 ]
Chen, Bowen [1 ]
Ji, Shujiang [1 ]
Zhang, Chao [1 ]
Yan, Na [1 ]
机构：
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China
来源：
IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021) | 2021年
基金：
中国国家自然科学基金;
关键词：
NOISE;
D O I：
10.1109/A-SSCC53895.2021.9634839
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页数：3
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