Configuring multiple boundary scan chains for interconnect testing

At a board level design with boundary scans, interconnect testing can be conducted by loading test vectors to the boundary-scan driver cells and capture responses from the boundary-scan sensor cells. Since the boundary scan may serialize the test process, the overall test time can be reduced if multiple boundary scan chains are used. In that case, the test time depends on how the boundary scan chips are connected into multiple scan chains. This paper presents a technique based on the greedy strategy and the sorting technique of single boundary scan chain to minimize the test time for interconnects.