A preliminary study of molecular dynamics on reconfigurable computers

In this paper we investigate the performance of platform FPGAs on a compute-intensive, floating-point-intensive supercomputing application, Molecular Dynamics (MD). MD is a popular simulation technique to track interacting particles through time by integrating their equations of motion. One part of the MD algorithm: was implemented using the Fabric Generator (FG)[10] and mapped onto several reconfigurable logic arrays. FG is a Java-based toolset that greatly accelerates construction of the fabrics from an abstract technology independent representation. Our experiments used technology-independent IEEE 32-bit floating point operators[2] so that, the design could be easily re-targeted. Experiments were performed using both non-pipelined and pipelined floating point modules. We present results for the Altera Excalibur ARM System on a Programmable Chip (SoPC), the Altera Stratix EP1S80, and the Xilinx Virtex-II Pro 2VP50. The best results obtained were 5.69 GFlops at 80MHz (Altera Stratix EP1S80), and 4.47 GFlops at 82 MHz (Xilinx Virtex-II Pro 2VP50). Assuming a 10W power budget, these results compare very favorably to, a 4Gflop/60W processing/power rate for a modem Pentium, suggesting that reconfigurable logic can achieve high performance at low power on floating-point-intensive applications.