An autonomous multiple module clock synchronization methodology for SoC

被引：0

作者：

Mai, SD ^{[1
]}

Lune, HW ^{[1
]}

Hsu, RC ^{[1
]}

Su, C ^{[1
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Chungli 320, Taiwan

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The global clock synchronization is achieved autonomously; by (1) phase locking to a reference PN clock, (2) detecting the lead/lag for the neighbors, and (3) fine tuning its own phase according to the decision fed back from the neighbors. The chip has been implemented by TSMC 0.35um 1P4M digital process. An evaluation board of 5 modules has been implemented and measured. For an initial fitter of 200ps and skew of 800ps, the output fitter is 47ps and skew is 100ps after lock on a PC board environment.

引用

页码：39 / 42

页数：4

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