High Thermal Graphite TIM Solution Applied to Fan-Out Platform

被引:3
|
作者
Su, Pin-Jing [1 ]
Lin, Dan [1 ]
Lin, Shane [1 ]
Xu, Xi-Zhang [1 ]
Lin, Rung Jeng [1 ]
Hung, Liang-Yih [1 ]
Wang, Yu-Po [1 ]
机构
[1] Siliconware Precis Ind Co Ltd SPIL, Corp R&D, Taichung, Taiwan
关键词
HPC; Fan-out; Graphite TIM; Vertical Thermal Conductivity;
D O I
10.1109/ECTC51906.2022.00196
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In the 5G era, the high performance computing (HPC) products play a pivotal role in supporting big data computing, data center transmission and networking applications. For computing performance enhancement, there are two development trends of product design including chip integration and high thermal dissipation. First, integrating the high bandwidth memory (HBM) into the package is a way to achieve both short and high-speed data transmission. In industry, fan-out platform can provide the benefit for die to die interconnection with fine line and the fine pitch bump design. Second, HPC devices bring high power consumption and require a thermal interface material (TIM) with high thermal conductivity for junction temperature reduction of SoC chip, due to the higher junction temperature will have work fail risk of SoC and even affect the nearby HBM. For high thermal TIM, the thermal conductivity of graphite TIM is directional, XY and Z axis are around 10W/mK and 20W/mK, respectively. The heat dissipation are not only through the vertical direction but also partially through the horizontal direction to the surroundings. The outstanding vertical thermal conductivity can effectively reduce the heat from SoC hot spot and reduce the thermal impact on HBM. Compared with normal FCBGA platform, a way to evaluate graphite TIM in FO structure is provided in this study. The maximum junction temperature impact of SoC and HBM is being explored from thermal simulation between different SoC hot spot design including uniform, center and corner conditions. In addition, the top exposed surface of chip module includes multiple interface with silicon and epoxy molding compound (EMC). We address the graphite TIM attaching performance and TIM coverage. Furthermore, through the innovative structure design to add the adhesive around the chip module, TIM coverage can be improved, especially for large package with worse warpage. All of the silicon die, EMC and underfill are pass without crack from SEM inspection, even if a larger HS (Heat Spreader) clamping force is required for graphite TIM. Finally, we have finished and passed the PLR (Package Level Reliability) with temperature cycle test (TCT) and unbiased highly accelerated stress test (uHAST) conditions.
引用
收藏
页码:1224 / 1227
页数:4
相关论文
共 50 条
  • [1] A New Semiconductor Package Design Flow and Platform Applied on High Density Fan-out Chip
    Wang, Chen-Chao
    Huang, Chih-Yi
    Chang, Keng-Tuan
    Lin, Youle
    IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, : 112 - 117
  • [2] Solution of Design Induced Reliability Risk for High Density Fan-Out packages
    Lin, Yu-Ting
    Lin, Yi-Sheng
    Hsiao, Yu-Hsiang
    2019 IEEE 21ST ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2019, : 95 - 98
  • [3] Electrical, Thermal, and Mechanical Characterization of eWLB, Fully Molded Fan-Out Package, and Fan-Out Chip Last Package
    Shih, Mengkai
    Huang, Chih-Yi
    Chen, Tsan-Hsien
    Wang, Chen-Chao
    Tarng, David
    Hung, C. P.
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2019, 9 (09): : 1765 - 1775
  • [4] High Gain and Wideband Antenna-in-Package Solution Using Fan-Out Technology
    Zhang, Xuesong
    Wang, Qian
    Xia, Chenhui
    Zhou, Chaojie
    Wang, Gang
    Cai, Jian
    JOURNAL OF ELECTRONIC PACKAGING, 2023, 145 (03)
  • [5] Electrical and Thermal Simulation of SWIFT™ High-density Fan-out PoP Technology
    Zwenger, Curtis
    Scott, George
    Baloglu, Bora
    Kelly, Mike
    Do, WonChul
    Lee, WonGeol
    Yi, JiHun
    2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 1962 - 1967
  • [6] Memristor Based High Fan-out Logic Gates
    Revanna, Nagaraja
    Swartzlander, Earl E., Jr.
    2016 IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE (DCAS), 2016,
  • [7] Fan-out Wafer Level Packaging - A Platform for Advanced Sensor Packaging
    Braun, Tanja
    Becker, Karl-Friedrich
    Hoelck, Ole
    Voges, Steve
    Kahle, Ruben
    Graap, Pascal
    Woehrmann, Markus
    Aschenbrenner, Rolf R.
    Dreissigacker, Marc
    Schneider-Ramelow, Martin
    Lang, Klaus-Dieter
    2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2019, : 861 - 867
  • [8] Rigorous coupled-wave method applied to fan-out gratings
    Restall, EJ
    Walker, AC
    IEE PROCEEDINGS-OPTOELECTRONICS, 1998, 145 (03): : 165 - 169
  • [9] Thermal Effect on Fan-out Wafer Level Package Strength
    Xu, Cheng
    Zhong, Z. W.
    Choi, W. K.
    PROCEEDINGS OF THE 2016 IEEE 18TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2016, : 700 - 703
  • [10] Reliability Study of Large Fan-Out BGA Solution on FinFET Process
    Yu, C. K.
    Chiang, W. S.
    Huang, P. S.
    Lin, M. Z.
    Fang, Y. H.
    Lin, M. J.
    Peng, Cooper
    Lin, Benson
    Huang, Michael
    2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 1623 - 1627