Architectural enhancements for Montgomery multiplication on embedded RISC processors

被引：0

作者：

Grossschädl, J ^{[1
]}

Kamendje, GA ^{[1
]}

机构：

[1] Graz Univ Technol, Inst Appl Informat Proc & Commun, A-8010 Graz, Austria

来源：

APPLIED CRYPTOGRAPHY AND NETWORK SECURITY, PROCEEDINGS | 2003年 / 2846卷

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Montgomery multiplication normally spends over 90% of its execution time in inner loops executing some kind of multiply-and-add operations. The performance of these critical code sections can be greatly improved by customizing the processor's instruction set for low-level arithmetic functions. In this paper, we investigate the potential of architectural enhancements for multiple-precision Montgomery multiplication according to the so-called Finely Integrated Product Scanning (FIPS) method. We present instruction set extensions to accelerate the FIPS inner loop operation based on the availability of a multiply/accumulate (MAC) unit with a wide accumulator. Finally, we estimate the execution time of a 1024-bit Montgomery multiplication on an extended MIPS32 core and discuss the impact of the multiplier latency.

引用

页码：418 / 434

页数：17

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