Cooperative communication based barrier synchronization in on-chip mesh architectures

被引:3
|
作者
Chen, Xiaowen [1 ,2 ]
Lu, Zhonghai [2 ]
Jantsch, Axel [2 ]
Chen, Shuming [1 ]
Liu, Hai [1 ]
机构
[1] Natl Univ Def Technol, Changsha 410073, Hunan, Peoples R China
[2] KTH Royal Inst Technol, S-16440 Stockholm, Sweden
来源
IEICE ELECTRONICS EXPRESS | 2011年 / 8卷 / 22期
基金
中国国家自然科学基金;
关键词
cooperative communication; barrier synchronization;
D O I
10.1587/elex.8.1856
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We propose cooperative communication as a means to enable efficient and scalable barrier synchronization on mesh-based many-core architectures. Our approach is different from but orthogonal to conventional algorithm-based optimizations. It relies on collaborating routers to provide efficient gather and multicast communication. In conjunction with a master-slave algorithm, it exploits the mesh regularity to achieve efficiency. The gather and multicast functions have been implemented in our router. Synthesis results suggest marginal area overhead. With synthetic and benchmark experiments, we show that our approach significantly reduces synchronization completion time and increases speedup.
引用
收藏
页码:1856 / 1862
页数:7
相关论文
共 50 条
  • [1] On-chip communication architectures for reconfigurable system-on-chip
    Lee, AS
    Bergmann, NW
    [J]. 2003 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS, 2003, : 332 - 335
  • [2] Fast exploration of bus-based on-chip communication architectures
    Pasricha, S
    Dutt, N
    Ben-Romdhane, M
    [J]. INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS, 2004, : 242 - 247
  • [3] A hierarchical modeling framework for on-chip communication architectures
    Zhu, XP
    Malik, S
    [J]. IEEE/ACM INTERNATIONAL CONFERENCE ON CAD-02, DIGEST OF TECHNICAL PAPERS, 2002, : 663 - 670
  • [4] Hybrid On-Chip Communication Architectures Heterogeneous Manycore Systems
    Joardar, Biresh Kumar
    Doppa, Janardhan Rao
    Pande, Partha Pratim
    Marculescu, Diana
    Marculescu, Radu
    [J]. 2018 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) DIGEST OF TECHNICAL PAPERS, 2018,
  • [5] Design space exploration for optimizing on-chip communication architectures
    Lahiri, K
    Raghunathan, A
    Dey, S
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (06) : 952 - 961
  • [6] Cross By Pass-Mesh Architecture for on-Chip Communication
    Gulzari, Usman Ali
    Anjum, Sheraz
    Agha, Shahrukh
    [J]. 2015 IEEE 9TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANYCORE SYSTEMS-ON-CHIP (MCSOC), 2015, : 267 - 274
  • [7] Genetic Algorithm Based On-Chip Communication Link Reconfiguration for Efficient On-Chip Communication
    Hemalatha, S. Beulah
    Vigneswaran, T.
    [J]. 2017 INTERNATIONAL CONFERENCE ON ALGORITHMS, METHODOLOGY, MODELS AND APPLICATIONS IN EMERGING TECHNOLOGIES (ICAMMAET), 2017,
  • [8] Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs
    Chen, Xiaowen
    Lu, Zhonghai
    Jantsch, Axel
    Chen, Shuming
    Guo, Yang
    Liu, Hengzhu
    [J]. IEICE ELECTRONICS EXPRESS, 2014, 11 (18): : 1 - 10
  • [9] Minimizing virtual channel buffer for routers in on-chip communication architectures
    Al Faruque, Mohammad Abdullah
    Henkel, Joerg
    [J]. 2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3, 2008, : 1080 - 1085
  • [10] A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs
    Zhu, Xinping
    Malik, Sharad
    [J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2007, 12 (01)