Ultra-low power analogue CMOS vision chip

被引：0

作者：

Jakusz, Jacek ^{[1
,2
]}

Jendernalik, Waldemar ^{[1
,2
]}

Blakiewicz, Grzegorz ^{[1
,2
]}

Piotrowski, Robert ^{[1
,2
]}

Szczepanski, Stanislaw ^{[1
,2
]}

机构：

[1] Gdansk Univ Technol, Dept Microelect Syst, PL-80233 Gdansk, Poland

[2] Gdansk Tech Univ, Katedra System Mikroelekt, Gdansk, Poland

来源：

PRZEGLAD ELEKTROTECHNICZNY | 2011年 / 87卷 / 10期

关键词：

CMOS analogue circuits; image processing; analogue processors;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper presents a project and results of testing of an analogue vision chip, which performs low-level convolutional image processing algorithms in real time. The prototype chip is implemented in 0.35 mu m CMOS technology, contains SIMD matrix of analogue processing elements of size 64 x 64. The dimensions of the matrix topography is 2.2 mm x 2.2 mm, giving the density of 877 processors per mm(2). Matrix dissipates less than 0.4 mW of power under 3.3 V supply and at the speed of image processing 100 frames/s.

引用

页码：88 / 91

页数：4

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