A low-power subscriber line interface circuit in a high-voltage CMOS technology

被引：0

作者：

Vahidfar, M ^{[1
]}

Tajalli, A ^{[1
]}

Atarodi, M ^{[1
]}

机构：

[1] Sharif Univ Technol, Dept Elect Engn, Tehran, Iran

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS | 2002年

关键词：

CMOS; Subscriber Line Interface Circuit (SLIC);

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low-power CMOS Subscriber Line Interface Circuit in a 1-um high voltage technology is presented. A systematic approach to extract the necessary specification for each block to achieve stability, accuracy, and other desired SLIC characteristics is applied. For this purpose a proper sense and feed system is introduced. The proposed SLIC shows a longitudinal balance of 53.7 dB while consumes 2.5 mA current with 16 mm(2) area. This transformer-less SLIC met transmission specifications without trimming.

引用

页码：409 / 412

页数：4

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