Ge p-MOSFETs With Scaled ALD La2O3/ZrO2 Gate Dielectrics

被引：18

作者：

Henkel, C. ^{[1
]}

Abermann, S. ^{[2
]}

Bethge, O. ^{[1
]}

Pozzovivo, G. ^{[1
]}

Klang, P. ^{[1
]}

Reiche, M. ^{[3
]}

Bertagnolli, E. ^{[1
]}

机构：

[1] Vienna Univ Technol, Inst Solid State Elect, A-1040 Vienna, Austria

[2] AIT Austrian Inst Technol GmbH, Dept Energy, A-1210 Vienna, Austria

[3] Max Planck Inst Microstruct Phys, D-06120 Halle, Germany

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2010年 / 57卷 / 12期

基金：

奥地利科学基金会;

关键词：

Atomic layer deposition (ALD); germanium; La2O3; MOSFET; ZrO2; HIGH-PERFORMANCE; ZRO2; PHASE; GERMANIUM; LAYER; DEVICES; STABILIZATION; DEPOSITION; OXIDES; FETS;

D O I：

10.1109/TED.2010.2081366

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Dielectric thin films of La2O3/ZrO2 deposited by atomic layer deposition (ALD) are investigated to be employed in Ge Schottky barrier p-MOSFETs. La2O3 is used as a thin passivation layer and is capped by atomic-layer-deposited ZrO2 as a gate dielectric. As the gate contact TiN capped by W is applied, midgap-level trap densities of similar to 3-4 x 10(12) eV(-1) cm(-2) and subtreshold slopes down to 115-120 mV/dec are achieved. The devices show negative threshold voltages of -0.5 to -0.6 V, as well as peak hole mobility values of similar to 50-75 cm(2)/V . s. Equivalent oxide thickness (EOT) is reduced to 0.96 nm upon postmetallization annealing without degrading the interface properties. The results show the scaling potential of the ALD La2O3 interlayer capped with ZrO2 gate dielectrics for the integration into sub-1-nm EOT Ge p-MOSFET devices.

引用

页码：3295 / 3302

页数：8

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