Incremental High-Level Synthesis

被引:0
|
作者
Lavagno, Luciano
Kondratyev, Alex
Watanabe, Yosinori
Zhu, Qiang
Fujii, Mototsugu
Tatesawa, Mitsuru
Nakayama, Noriyasu
机构
关键词
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The widespread acceptance of High-level synthesis as a mainstream tool mostly depends on its tight integration with the following RTL-to-GDSII design flow. A key aspect is the handling of so-called Engineering Change Orders (ECOs), i.e. minor changes required to fix small functional bugs or meet performance requirements late in the design cycle. Traditional high-level synthesis has attempted to optimize at best the output logic. However, in the ECO scenario the goal is to implement the required change with as few modifications as possible to the RTL, logic netlist, placed netlist and layout. In this paper we show how, by judiciously changing the internal databases used by the tool to match as much as possible the original design, one can achieve minimal impact and implement ECOs in truly incremental mode, while full-blow re-synthesis would lead to massive unnecessary downstream changes. The tool essentially matches source constructs between the original and the ECO design, and copies as many synthesis decisions as possible from the original design to the ECO design.
引用
收藏
页码:693 / 698
页数:6
相关论文
共 50 条
  • [1] Unified incremental physical-level and high-level synthesis
    Gu, Zhenyu
    Wang, Ha
    Dick, Robert P.
    Zhou, Hai
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (09) : 1576 - 1588
  • [2] HIGH-LEVEL DEBUGGING WITH THE AID OF AN INCREMENTAL OPTIMIZER
    POLLOCK, LL
    SOFFA, ML
    PROCEEDINGS OF THE TWENTY-FIRST, ANNUAL HAWAII INTERNATIONAL CONFERENCE ON SYSTEM SCIENCES, VOLS 1-4: ARCHITECTURE TRACK, SOFTWARE TRACK, DECISION SUPPORT AND KNOWLEDGE BASED SYSTEMS TRACK, APPLICATIONS TRACK, 1988, : B524 - B532
  • [3] A novel incremental floorplan algorithm for duplication in integration of high-level synthesis and floorplan
    Dai, Hui
    Bian, Jinian
    Zhou, Qiang
    Liu, Zhipeng
    2007 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEMS; VOL 2: SIGNAL PROCESSING, COMPUTATIONAL INTELLIGENCE, CIRCUITS AND SYSTEMS, 2007, : 1163 - +
  • [4] Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support
    Schafer, Benjamin Carrion
    IEEE EMBEDDED SYSTEMS LETTERS, 2015, 7 (02) : 51 - 54
  • [5] HIGH-LEVEL SYNTHESIS
    PAWLAK, A
    MICROPROCESSING AND MICROPROGRAMMING, 1992, 35 (1-5): : 261 - 261
  • [6] KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design
    Piccolboni, Luca
    Di Guglielmo, Giuseppe
    Carloni, Luca P.
    2019 FORMAL METHODS IN COMPUTER AIDED DESIGN (FMCAD), 2019, : 105 - 109
  • [7] Validating High-Level Synthesis
    Kundu, Sudipta
    Lerner, Sorin
    Gupta, Rajesh
    COMPUTER AIDED VERIFICATION, 2008, 5123 : 459 - 472
  • [8] OPTIMIZATIONS IN HIGH-LEVEL SYNTHESIS
    ROSENSTIEL, W
    MICROPROCESSING AND MICROPROGRAMMING, 1986, 18 (1-5): : 347 - 352
  • [9] HIGH-LEVEL SYNTHESIS - A TUTORIAL
    WU, ACH
    LIN, YL
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1995, E78D (03) : 209 - 218
  • [10] ALGORITHMS FOR HIGH-LEVEL SYNTHESIS
    PAULIN, PG
    KNIGHT, JP
    IEEE DESIGN & TEST OF COMPUTERS, 1989, 6 (06): : 18 - 31