"Zeppelin": An SoC for Multichip Architectures

被引:37
|
作者
Burd, Thomas [1 ]
Beck, Noah [3 ]
White, Sean [3 ]
Paraschou, Milam [4 ]
Kalyanasundharam, Nathan [2 ]
Donley, Gregg [1 ]
Smith, Alan [6 ]
Hewitt, Larry [7 ]
Naffziger, Samuel [5 ]
机构
[1] Adv Micro Devices Inc, Santa Clara, CA 95054 USA
[2] Adv Micro Devices Inc, AMDs Infin Fabr IF, Santa Clara, CA 95054 USA
[3] Adv Micro Devices Inc, Boxboro, MA 01719 USA
[4] Adv Micro Devices Inc, PCIe Design, Ft Collins, CO 80528 USA
[5] Adv Micro Devices Inc, Ft Collins, CO 80528 USA
[6] Adv Micro Devices Inc, Infin Fabr IF Architecture Team, Austin, TX 78735 USA
[7] Adv Micro Devices Inc, Power Management Architecture Microprocessor Prod, Austin, TX 78735 USA
关键词
14; nm; high-frequency design; microprocessors; multi-chip module (MCM); scalable fabric; system-on-achip (SoC) architecture;
D O I
10.1109/JSSC.2018.2873584
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
AMD's "Zeppelin" system-on-a-chip (SoC) combines eight high-performance "Zen" cores with a shared 16-MB L3 Cache, along with six high-speed I/O links and two DDR4 channels, using the infinity fabric (IF) to provide a high speed, low latency, and power-efficient connectivity solution. This solution allows the same SoC silicon die to be designed into three separate packages and provides highly competitive solutions in three different market segments. IF is critical to this high-leverage design re-use, utilizing a coherent, scalable data fabric (SDF) for on-die communication, as well as inter-die links, extending up to eight dies across two packages. To support this scalability, an energy efficient, custom physical-layer link was designed for in-package, high-speed communication between the dies. Using an additional scalable control fabric (SCF), a hierarchical power and system management unit (SMU) was used to monitor and manage a distributed set of dies to ensure the products stay within infrastructure limits. It was essential that the floor plan of the SoC was co-designed with the package substrate. The SoC used a 14-nm FinFET process technology and contains 4.8B transistors on a 213 mm(2) die.
引用
收藏
页码:133 / 143
页数:11
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