Low power, high speed, charge recycling CMOS threshold logic gate

被引：36
|
作者：
Celinski, P
López, JF
Al-Sarawi, S
Abbott, D
机构：
[1] Univ Adelaide, Dept Elect & Elect Engn, Ctr High Performance Integrated Technol & Syst, Adelaide, SA 5005, Australia
[2] Univ Las Palmas G C, Res Inst Appl Microelect, Las Palmas Gran Canaria 35017, Spain
来源：
ELECTRONICS LETTERS | 2001年 / 37卷 / 17期
关键词：
D O I：
10.1049/el:20010742
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.
引用
收藏
页码：1067 / 1069
页数：3
相关论文
共 50 条
  • [1] Low-power CMOS threshold-logic gate
    Avedillo, MJ
    Quintana, JM
    Rueda, A
    Jimenez, E
    ELECTRONICS LETTERS, 1995, 31 (25) : 2157 - 2159
  • [2] A high speed low power CMOS clock driver using charge recycling technique
    Bouras, I
    Liaperdos, Y
    Arapoyanni, A
    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 657 - 660
  • [3] Race-free CMOS Pass-gate Charge Recycling Logic (FCPCL) for low power applications
    Abbasian, A
    Rasouli, SH
    Derakhshandeh, J
    Afzali-Kusha, A
    Nourani, M
    2003 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, 2003, : 87 - 89
  • [4] CMOS differential logic family with self-timing and charge-recycling for high-speed and low-power VLSI
    Kong, BS
    Im, JD
    Kim, YC
    Jang, SJ
    Jun, YH
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2003, 150 (01): : 45 - 50
  • [5] Area efficient, high speed parallel counter circuits using charge recycling threshold logic
    Celinski, P
    Abbott, D
    Cotofana, SD
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMS, 2003, : 233 - 236
  • [6] NEW HIGH-SPEED CMOS LOGIC - FASTER SPEED AND LOW-POWER
    CRAIG, S
    ELECTRONIC ENGINEERING, 1981, 53 (660): : 29 - &
  • [7] A High speed Low Power Adder in Dynamic logic base on Transmission Gate
    Jain, Neeraj
    Gour, Puran
    Shrman, Brahmi
    2015 INTERNATIONAL CONFERENCED ON CIRCUITS, POWER AND COMPUTING TECHNOLOGIES (ICCPCT-2015), 2015,
  • [8] CMOS pass-gate no-race charge-recycling logic (CPNCL)
    Yoo, Seung-Moon
    Kang, Sung-Mo
    Proceedings - IEEE International Symposium on Circuits and Systems, 1999, 1
  • [9] CMOS Pass-gate No-race Charge-recycling Logic (CPNCL)
    Yoo, SM
    Kang, SM
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI, 1999, : 226 - 229
  • [10] Design of low power CMOS drivers based on charge recycling
    KyriakisBitzaros, ED
    Nikolaidis, SS
    ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 1924 - 1927
12345