A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction

被引:0
|
作者
Junsangsri, Pilin [1 ]
Lombardi, Fabrizio [1 ]
Han, Jie [2 ]
机构
[1] Northeastern Univ, Elect & Comp Engn, Boston, MA 02115 USA
[2] Univ Alberta, Elect & Comp Engn, Edmonton, AB, Canada
来源
2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE) | 2014年
关键词
Memory Cell; Programmable Metallization Cell (PMC); SEU; Detection; Correction; Emerging Technology; MEMORY CELL; DESIGNS; UPSET;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for SEU tolerance. The proposed NVSRAM cell consists of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has concurrent error detection (CED) and correction capabilities; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation; data from the non-volatile memory element is copied back to the SRAM core. The dual-rail checker utilizes two XOR gates each made of 2 inverters and 2 ambipolar transistors, hence, it has a hybrid nature. Extensive simulation results are provided. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit such as delay and circuit complexity and thus applicable to integrated circuits such as FPGAs requiring secure on-chip non-volatile storage (i.e. LUTs) for multi-context configurability.
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页数:4
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