Design and investigation of gate-to-gate passive interconnections for SFQ logic circuits

被引：14

作者：

Hashimoto, Y ^{[1
]}

Yorozu, S

Kameda, Y

Fujimaki, A

Terai, H

Yoshikawa, N

机构：

[1] Int Superconduct Technol Ctr, Superconduct Res Lab, Ibaraki 3058501, Japan

[2] Nagoya Univ, Nagoya, Aichi 4648603, Japan

[3] Natl Inst Informat & Commun Technol, Kobe, Hyogo 6512492, Japan

[4] Yokohama Natl Univ, Yokohama, Kanagawa 2408501, Japan

来源：

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY | 2005年 / 15卷 / 03期

关键词：

integrated circuit; interconnection; passive transmission line; single-flux-quantum (SFQ); superconductor;

D O I：

10.1109/TASC.2005.847487

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a method of designing single-flux-quantum (SFQ) logic circuits with passive gate-to-gate interconnections. Based on our method, we designed a 2 x 2 switch in which all the interconnections are implemented with passive transmission lines (PTLs) while short Josephson transmission line (JTL) segments are used only to adjust the signal timings. Compared with an identical switch using JTL interconnections, the switch using PTL interconnections has 45 % fewer wiring junctions and requires 48% less wiring power current. The switch operated at 40 GHz with a bias margin of +/- 9.5%.

引用

页码：3814 / 3820

页数：7

共 50 条

[1] NAND gate for SFQ logic circuits
Myoren, H
Ono, S
Takada, S
IEICE TRANSACTIONS ON ELECTRONICS, 2000, E83C (01) : 81 - 84
[2] Transmission Line Effects of Long Gate-to-Gate Interconnections in Adiabatic Quantum-Flux-Parametron Logic Circuits
Asai, Kazuhito
Takeuchi, Naoki
Suzuki, Hideo
Yamanashi, Yuki
Yoshikawa, Nobuyuki
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2022, 32 (07)
[3] Investigation for the basic characteristics of HTS SFQ logic gate
Saitoh, Kazuo
Utagawa, Tadashi
Enomoto, Youichi
IEEE Transactions on Applied Superconductivity, 1999, 9 (2 III): : 3837 - 3840
[4] Investigation for the basic characteristics of HTS SFQ logic gate
Saitoh, K
Utagawa, T
Enomoto, Y
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 1999, 9 (02) : 3837 - 3840
[5] Analysis and Stabilization of Signal Reflections in Gate-to-Gate Connections for AQFP Circuits
Johnston, Michael A. A.
Ayala, Christopher L. L.
Tanaka, Tomoyuki
Yoshikawa, Nobuyuki
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2023, 33 (05)
[6] An Optimal Gate Design for the Synthesis of Ternary Logic Circuits
Kim, Sunmean
Lim, Taeho
Kang, Seokhyeong
2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2018, : 476 - 481
[7] ASTABLES - LOGIC GATE CIRCUITS
WILLIAMS, P
WIRELESS WORLD, 1980, 86 (1529): : 92 - 93
[8] Design and demonstration of pipelined circuits using SFQ logic
Akahori, Akira
Sekiya, Akito
Yamada, Takahiro
Fujimaki, Akira
Hayakawa, Hisao
IEICE Transactions on Electronics, 2002, E85-C (03) : 641 - 644
[9] Design and demonstration of pipelined circuits using SFQ logic
Akahori, A
Sekiya, A
Yamada, T
Fujimaki, A
Hayakawa, H
IEICE TRANSACTIONS ON ELECTRONICS, 2002, E85C (03): : 641 - 644
[10] A DESIGN PROCEDURE FOR RADIATION HARDENING CERTAIN NOR GATE LOGIC CIRCUITS
MAURER, HE
IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1967, EC16 (04): : 519 - &

← 1 2 3 4 5 →