GPUOPT: Power-efficient Photonic Network-on-Chip for a Scalable GPU

被引:3
|
作者
Bashir, Janibul [1 ]
Sarangi, Smruti R. [2 ]
机构
[1] Indian Inst Technol, Dept Comp Sci & Engn, New Delhi 110016, India
[2] Indian Inst Technol, Dept Comp Sci & Engn, Dept Elect Engn, New Delhi 110016, India
关键词
On-chip networks; photonics; static power consumption; GPUs; DESIGN SPACE; INTERCONNECTION; LASER;
D O I
10.1145/3416850
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
On-chip photonics is a disruptive technology, and such NoCs are superior to traditional electrical NoCs in terms of latency, power, and bandwidth. Hence, researchers have proposed a wide variety of optical networks for multicore processors. The high bandwidth and low latency features of photonic NoCs have led to the overall improvement in the system performance. However, there are very few proposals that discuss the usage of optical interconnects in Graphics Processor Units (GPUs). GPUs can also substantially gain from such novel technologies, because they need to provide significant computational throughput without further stressing their power budgets. The main shortcoming of optical networks is their high static power usage, because the lasers are turned on all the time by default, even when there is no traffic inside the chip, and thus sophisticated laser modulation schemes are required. Such modulation schemes base their decisions on an accurate prediction of network traffic in the future. In this article, we propose an energy-efficient and scalable optical interconnect for modern GPUs called GPUOPT that smartly creates an overlay network by dividing the symmetric multiprocessors (SMs) into clusters. It furthermore has separate sub-networks for coherence and non-coherence traffic. To further increase the throughput, we connect the off-chip memory with optical links as well. Subsequently, we show that traditional laser modulation schemes (for reducing static power consumption) that were designed for multicore processors are not that effective for GPUs. Hence, there was a need to create a bespoke scheme for predicting the laser power usage in GPUs. Using this set of techniques, we were able to improve the performance of a modern GPU by 45% as compared to a state-of-the-art electrical NoC. Moreover, as compared to competing optical NoCs for GPUs, our scheme reduces the laser power consumption by 67%, resulting in a net 65% reduction in ED2 for a suite of Rodinia benchmarks.
引用
收藏
页数:26
相关论文
共 50 条
  • [1] Power Efficient Photonic Network-on-Chip for a Scalable GPU
    Bashir, Janibul
    Sethi, Khushal
    Sarangi, Smruti R.
    PROCEEDINGS OF THE 13TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS'19), 2019,
  • [2] LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip
    Li, Cheng
    Browning, Mark
    Gratz, Paul V.
    Palermo, Samuel
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2014, 33 (06) : 826 - 838
  • [3] Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation
    Effiong, Charles
    Sassatelli, Gilles
    Gamatie, Abdoulaye
    MICROPROCESSORS AND MICROSYSTEMS, 2018, 60 : 173 - 184
  • [4] Area and Power-efficient Innovative Network-on-Chip Architecurte
    Wang, Chifeng
    Hu, Wen-Hsiang
    Bagherzadeh, Nader
    Lee, Seung Eun
    PROCEEDINGS OF THE 18TH EUROMICRO CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING, 2010, : 533 - 539
  • [5] Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip
    Zheng, Yan
    Lisherness, Peter
    Gao, Ming
    Bovington, Jock
    Cheng, Kwang-Ting
    Wang, Hong
    Yang, Shiyuan
    JOURNAL OF OPTICAL COMMUNICATIONS AND NETWORKING, 2012, 4 (12) : 955 - 966
  • [6] LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip for Future Parallel Architectures
    Li, Cheng
    Browning, Mark
    Gratz, Paul V.
    Palermo, Samuel
    PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT'12), 2012, : 421 - 422
  • [7] UBERNoC: Unified Buffer Power-Efficient Router for Network-on-Chip
    Farrokhbakht, Hossein
    Kao, Henry
    Jerger, Natalie Enright
    PROCEEDINGS OF THE 13TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS'19), 2019,
  • [8] Silicon-Photonic Network Architectures for Scalable, Power-Efficient Multi-Chip Systems
    Koka, Pranay
    McCracken, Michael O.
    Schwetman, Herb
    Zheng, Xuezhe
    Ho, Ron
    Krishnamoorthy, Ashok V.
    ISCA 2010: THE 37TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, 2010, : 117 - 128
  • [9] A Power-Efficient Network-on-Chip for Multi-core Stream Processors
    Jiang, Guoyue
    Wang, Fang
    Li, Zhaolin
    Wei, Shaojun
    2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
  • [10] Power Network-on-Chip for Scalable Power Delivery
    Vaisband, Inna
    Friedman, Eby G.
    2014 ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM LEVEL INTERCONNECT PREDICTION (SLIP), 2014,