A high-speed and high-precision Winner-Select-Output (WSO) ASIC

被引：6

作者：

Yu, HM ^{[1
]}

Miyaoka, RS ^{[1
]}

Lewellen, TK ^{[1
]}

机构：

[1] Univ Washington, Med Ctr, Seattle, WA 98195 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1998年 / 45卷 / 03期

关键词：

D O I：

10.1109/23.682634

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design and performance characteristics of a 16-channel Winner-Select-Output (WSO) ASIC are presented. The WSO ASIC does a fast comparison of 16 analog input voltages, outputs the maximum signal, the "second" maximum (partner) signal, and their addresses. The WSO ASIC chip is a key component of an analog electronics system being developed for a depth of interaction (DOT) PET detector module. The basic cell of the WSO ASIC is a "winner take all" (WTA) circuit. The precision of the WSO ASIC is enhanced by using a cascade structure WTA cell. The chip requires a single +5V supply and consumes 35 mW of power. The WSO ASIC is sensitive to voltage differences as small as 10 mV. The propagation delay of the chip is less than 30 nsec for voltage differences of >50 mV (typical for proposed application).

引用

页码：772 / 776

页数：5

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