A software engineering methodology to optimize caching in multi-processor DSP architectures: TMS320C80 results towards the real-time execution of low level image processing

This paper introduces an original software engineering methodology we developed while focusing on the implementation of a low-level image processing library targeted for a shared memory multi-processor DSP architecture: the TMS320C80. Real-time constraints led us to concentrate on the enhancement of data locality thanks to the software managing of caches based on an advanced multi-dimensional DMA. This contribution compares to other existing C80's image processing libraries [1][2] in terms of genericity, flexibility, and performance improvement. Our approach allows for the composing of concurrent processing chains grounded on a modular library gathering basic processing operators. Generic mechanisms allow to address all basic operator's requirements as well as to quickly expand the library thanks to a re-usable and well defined framework. Flexibility allows to dynamically re-configure a chain or to modify the region of interest and the number of processors. We finally demonstrate experimentally that our approach allows significant performance improvements.