A generic methodology for the software managing of caches in multi-processors DSP architectures - Application to the real-time implementation of low level image processing on the TMS320C80

This article introduces a novel software engineering methodology designed for the real-time execution of low-level image operators running on multi-processors DSP architectures. We detail the results we gained while implementing our approach on the TMS320C80, a shared memory multiprocessors architecture [1]. Our contribution compares to other existing C80's image processing libraries [2][3] in terms of genericity, flexibility, and performance improvement. More specifically, generic mechanisms allow to address various operator's requirements as well as expanding them using a standard framework. Our approach is flexible enough to allow for the dynamic composing of concurrent and reconfigurable processing chains thanks to a modular library implementing basic operators. Processing chains work on various image sizes and with any number of processors. Above all, our methodology permits performance improvement by enhancing data locality.