Study on Energy Efficient Burn-In Techniques for Power Supplies

被引:0
|
作者
Narayanan, Praveen [1 ]
Mini, V. P. [1 ]
机构
[1] Coll Engn Trivandrum, Dept Elect & Elect Engn, Trivandrum, Kerala, India
关键词
burn-in technique; efficiency; energy recycling; SYSTEM;
D O I
暂无
中图分类号
X [环境科学、安全科学];
学科分类号
08 ; 0830 ;
摘要
Energy conservation is of utmost importance in this modern era. However saving energy during the initial burn-in phase of a product is an area with very few advances in research. Recent trends have introduced the concept of energy recycling during this phase as well. Traditional burn-in methods using resistor load banks wastes electricity besides raising room temperatures. This paper presents high efficiency energy-recyclable burn-in technologies for power supplies which reduces power wastage. Different burn in techniques for dc power supplies based on efficiency are discussed which recycles most of the energy back to grid after testing. Energy efficient burn-in technique for UPS and electronic ballast with a high efficiency hysteresis inverter has also been proposed.
引用
收藏
页码:204 / 209
页数:6
相关论文
共 50 条
  • [21] Effects of burn-in stressing on radiation response of power VDMOSFETs
    Stojadinovic, N
    Djoric-Veljkovic, S
    Manic, I
    Davidovic, V
    Golubovic, S
    [J]. MICROELECTRONICS JOURNAL, 2002, 33 (11) : 899 - 905
  • [22] A family of converters for UPS production burn-in energy recovery
    Ayres, CA
    Barbi, I
    [J]. IEEE TRANSACTIONS ON POWER ELECTRONICS, 1997, 12 (04) : 615 - 622
  • [23] Design Guidelines for Energy Efficient AC to DC Power Supplies
    Chrysostomou, Michael
    Christofides, Nicholas
    Ioannou, Stelios
    Marouchos, Christos C.
    [J]. IECON 2021 - 47TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 2021,
  • [24] Energy-Recyclable Burn-In Technology for Electronic Ballasts
    Chen, Nan
    Shu-Hung, Henry
    [J]. IEEE TRANSACTIONS ON POWER ELECTRONICS, 2011, 26 (09) : 2550 - 2562
  • [25] Effect of static power dissipation in burn-in environment on yield of VLSI
    Vassighi, A
    Semenov, O
    Sachdev, M
    Keshavarzi, A
    [J]. 17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2002, : 12 - 19
  • [26] Power Management for Wafer-Level Test During Burn-In
    Bahukudumbi, Sudarshan
    Chakrabarty, Krishnendu
    [J]. PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 2008, : 231 - 236
  • [27] Maximization of power dissipation under random excitation for burn-in testing
    Huang, KC
    Lee, CL
    Chen, JE
    [J]. INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 567 - 576
  • [28] MINIMIZING POWER-SUPPLY DISTURBANCES DURING SEMICONDUCTOR BURN-IN
    MAIER, C
    [J]. EE-EVALUATION ENGINEERING, 1995, 34 (03): : 151 - 152
  • [29] Efficient battery power supplies
    Bateman, C
    [J]. ELECTRONICS WORLD, 2000, 106 (1770): : 460 - 464
  • [30] Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC
    Davide Appello
    Paolo Bernardi
    Conrad Bugeja
    Riccardo Cantoro
    Giorgio Pollaccia
    Marco Restifo
    Federico Venini
    [J]. Journal of Electronic Testing, 2018, 34 : 43 - 52