On adapting power estimation models for embedded soft-core processors

被引：1
|
作者：
de Holanda, Jose A. [1 ]
Assumpcao, Jecel, Jr. [1 ]
Wolf, Denis E. [1 ]
Marques, Eduardo [1 ]
Cardoso, Joao M. P. [2 ]
机构：
[1] Univ Sao Paulo, Dept Comp Syst, BR-13560 Sao Carlos, Brazil
[2] Univ Tecn Lisbon UTL, Inst Super Tecn IST, INESC ID, Lisbon, Portugal
来源：
2007 INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS | 2007年
关键词：
D O I：
10.1109/SIES.2007.4297358
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
The increasing use of battery-powered embedded systems has motivated the development of power consumption models in order to help designers to build low-power systems. Due to the configurability features of FPGAs, the adoption of systems containing one or more soft-core processors on a single chip is becoming more and more attractive. This paper presents an adaptation of the instruction-level power estimation model to soft-core processors implemented in FPGAs. This model allowed to estimate the power dissipated in eleven test applications with a maximum error of 4.78%. The Ongoing work includes efforts towards a software power estimation model for multi-core systems embedded in a single FPGA device.
引用
收藏
页码：345 / +
页数：2
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