Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution

被引：121
|
作者：
Kalisz, J
Szplet, R
Pasierbinski, J
Poniecki, A
机构：
[1] Military University of Technology
来源：
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT | 1997年 / 46卷 / 01期
关键词：
D O I：
10.1109/19.552156
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented, Time coding with 200-ps resolution (LSB), 10-ns range, and very short conversion time is realized by two tapped delay lines working in a differential mode, Thanks to the local feedback loops, the output from the delay line is obtained directly in ''1-out of-N'' code and then converted to 6-bit natural binary, Within the temperature range from 0 degrees C to 45 degrees C, the time offset at the output is constant, the resolution changes by +/- 0.02 LSB, and the offset corrected integral linearity error is less than 1 LSB.
引用
收藏
页码：51 / 55
页数：5
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