A new reconfigurable bit-serial systolic divider for GF(2M) and GF(P).

被引：0

作者：

Cohen, AE ^{[1
]}

Parhi, KK ^{[1
]}

机构：

[1] Univ Minnesota Twin Cities, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA

来源：

2005 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS 1-5: SPEECH PROCESSING | 2005年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper focuses on the design of a new dual field divider that can achieve performance of 1/m throughput. This dual field division unit can operate at 118 MHz with a latency of 7m - 2 cycles and has an area requirement 15 XOR2, 40 AN D2, 29 MUX2, and 7 INV gates per processing element with a total of 2m processing elements. It is intended to be used in an Elliptic Curve Crypto-Accelerator for GF(2(n)) and GF(p). The actual performance for scalar point multiplication in GF(2(571)) running at 100 MHz would be 20.4 kP/s. The actual performance for scalar point multiplication in GF(p) with broken vertical bar p broken vertical bar = 521 running at 100 MHz would be 24.4 kP/s.

引用

页码：105 / 108

页数：4

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