CMOS Ternary Logic With a Biristor Threshold Switch for Low Static Power Consumption

被引：5

作者：

Han, Joon-Kyu ^{[1
]}

Yu, Ji-Man ^{[1
]}

Nam, Seo-Yeon ^{[1
]}

Choi, Yang-Kyu ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol KAIST, Sch Elect Engn, Daejeon 34141, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2022年 / 43卷 / 07期

基金：

新加坡国家研究基金会;

关键词：

MOSFET; Multivalued logic; Logic gates; Latches; Switches; Voltage measurement; Threshold voltage; Biristor; biristor threshold switch (BTS); multi-valued logic (MVL); single transistor latch (STL); ternary logic; MULTIPLE-VALUED LOGIC; SYNTHESIS METHODOLOGY; VOLTAGE; TUTORIAL;

D O I：

10.1109/LED.2022.3172067

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A CMOS ternary logic is demonstrated using a biristor threshold switch (BTS). A biristor, which can operate as a threshold switch, encloses a two-terminal n-p-n structure with a floating p-base region akin to a base-open BJT. The switching mechanism is a single-transistor latch (STL). When a BTS and a MOSFET are serially connected, three stable states are sustained for a ternary logic system. Compared to other ternary devices, static power can be greatly reduced due to low leakage current of the BTS. In addition, the BTS and the MOSFET were co-integrated due to their homeomorphy for fabrication simplicity, i.e., because the BTS has a structure identical to that of a MOSFET, unlike other threshold switches.

引用

页码：1005 / 1008

页数：4

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