A High Performance Bitplane Encoder for the CCSDS 122.0-B-1 Compression Standard

被引：0
|
作者：
Kefalas, Nikoloas [1 ]
Theodoridis, George [1 ]
机构：
[1] Univ Patras, VLSI Design Lab, Elect & Comp Engn Dept, Rion 26500, Greece
来源：
2018 41ST INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS AND SIGNAL PROCESSING (TSP) | 2018年
关键词：
Biplane encoder; CCSDS-122.0-B-1; FPGA; Image Compression; Payload instruments; Space Applications;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a high performance Bitplane Encoder (BPE) architecture for the CCSDS 122.0-B-1 compression standard is proposed. Exploiting inherit parallelization features of the algorithm, the introduced architecture achieves processing rate equal to 1 cycle/sample. Also, it avoids performance bottlenecks during modelling, code option selection for symbol entropy coding and symbol packing for stream generation. At the same time, high frequency and throughput values are achieved by carefully placed pipeline stages. The architecture implemented on space Virtex 5 QV FPGA device and compared with similar ones. Based on the experimental results it is proved its superiority in terms of frequency and throughput.
引用
收藏
页码：327 / 333
页数：7
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