An image processing platform: RASH-IP

被引：0

作者：

Asami, H ^{[1
]}

Yamagishi, Y ^{[1
]}

Imai, T ^{[1
]}

Takimoto, T ^{[1
]}

Amano, K ^{[1
]}

Nakagawa, M ^{[1
]}

机构：

[1] 1 Mitsubishi Elect Corp, Kamakura, Kanagawa 2478501, Japan

来源：

SICE 2004 ANNUAL CONFERENCE, VOLS 1-3 | 2004年

关键词：

parallel processing; image processing; FPGA; reconfigurable computing;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We developed an image processing platform RASH-IP on the basis of development know-how of FPGA-based parallel machine RASH. RASH-IP contains six ALTERA Stratix (EPIS25) FPGAs on the VME board. RASH-IP boards have 10 buses in order to transfer HDTV video image data with several FPGAs. Each FPGA is directly connected to an 8M-byte synchronous SRAM so that it can hold the large amount of data. Moreover, RASH-IP boards have parallel 10 ports and serial 10 ports for image data transmission between boards. We examined an application of affine-transfer processing of video image data on RASH-IP.

引用

页码：1859 / 1862

页数：4

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