FPGA implementation of addition as a part of the convolution

被引：3
|
作者：
Jamro, E
Wiatr, K
机构：
来源：
EUROMICRO SYMPOSIUM ON DIGITAL SYSTEMS DESIGN, PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/DSD.2001.952368
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Addition is a fundamental operation for the convolution (FIR filters). In FPGAs, addition should be carried out in a standard way employing ripple-carry adders (rather than carry-save adders), which complicates search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of inputs to the adders tree have been considered, e.g. correlation between inputs, These parameters are specified in different ways for different convolver architectures: Multiplierless Multiplication, Look-Up Table based Multiplication, Distributed Arithmetic. Furthermore, optimisation techniques: Exhaustive Search and Greed), Algorithm have been implemented, and as a result, the Greedy Algorithm is the best solution when time of computation is of great importance. Otherwise, the Exhaustive Search should be employed for the number of the addition inputs n less than or equal to8. This paper is a part of the research on the AuToCon Automated Tool for generating Convolution in FPGAs.
引用
收藏
页码：458 / 465
页数：8
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