Low-complexity bit-parallel systolic architecture for computing AB2+C in a class of finite field GF(2m)

被引：23

作者：

Lee, CY ^{[1
]}

Lu, EH

Sun, LF

机构：

[1] Chang Gung Univ, Dept Elect Engn, Chungli 320, Taiwan

[2] Chung Hwa Telecommun Lab, Dept Program Coordinat, Chung Hwa, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 2001年 / 48卷 / 05期

关键词：

all one polynomial (AOP); finite field; latency; systolic multiplier;

D O I：

10.1109/82.938363

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An algorithm for computing AB(2) + C over a finite field GF(2(m)) is presented using the properties of the irreducible all one polynomial of degree m. Based on the algorithm, a parallel-in parallel-out systolic multiplier is proposed. The architecture of the multiplier is very simple, regular, modular, and exhibits very low latency and propagation delay. Therefore, it is suitable for very large scale integration implementation of cryptosystems.

引用

页码：519 / 523

页数：5

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