InFO (Wafer Level Integrated Fan-Out) Technology

被引:0
|
作者
Tseng, Chien-Fu [1 ]
Liu, Chung-Shi [1 ]
Wu, Chi-Hsi [1 ]
Yu, Douglas [1 ]
机构
[1] Taiwan Semicond Mfg Co R&D, 168 Pk Ave 2,Sci Based Ind Pk, Hsinchu, Taiwan
关键词
Fan-out; Wafer-Level Packaging; InFO_PoP; WLSI; Heterogeneous Integration; ELECTROMIGRATION;
D O I
10.1109/ECTC.2016.65
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore's Law for the smart mobile as well as internet of things (IoT) applications.
引用
收藏
页码:1 / 6
页数:6
相关论文
共 50 条
  • [1] CPI Advancement in Integrated Fan-Out (InFO) Technology
    Yu, Douglas
    Yeh, John
    Lin, Tsung-Shu
    Yee, K. C.
    [J]. 2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2017,
  • [2] High-Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System Integration
    Liu, Christianto C.
    Chen, Shuo-Mao
    Kuo, Feng-Wei
    Chen, Huan-Neng
    Yeh, En-Hsiang
    Hsieh, Cheng-Chieh
    Huang, Li-Hsien
    Chiu, Ming-Yen
    Yeh, John
    Lin, Tsung-Shu
    Yeh, Tzu-Jin
    Hou, Shang-Yun
    Hung, Jui-Pin
    Lin, Jing-Cheng
    Jou, Chewn-Pu
    Wang, Chuei-Tang
    Jeng, Shin-Puu
    Yu, Douglas C. H.
    [J]. 2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2012,
  • [3] Design of On-Chip Microwave Filters in Integrated Fan-Out Wafer Level Packaging (InFO-WLP) Technology
    Shen, Chi-Kai
    Tsai, Ming-Hsien
    Chen, Huan-Neng
    Jou, Chewn-Pu
    Liu, Sally
    Hsueh, Fu-Lung
    Wu, Tzong-Lin
    [J]. 2015 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC), 2015, : 246 - 248
  • [4] High Performance Passive Devices for Millimeter Wave System Integration on Integrated Fan-Out (InFO) Wafer Level Packaging Technology
    Tsai, Chung-Hao
    Hsieh, Jeng-Shien
    Lin, Wei-Heng
    Yen, Liang-Ju
    Hung, Jeng-Nan
    Peng, Tai-Hao
    Wang, Hsi-Ching
    Kuo, Cheng-Yu
    Huang, Issac
    Chu, Welling
    Lei, Yi-Yang
    Yu, C. H.
    Sheu, Lawrence C.
    Hsieh, Ching-Hua
    Liu, C. S.
    Yee, Kuo-Chung
    Wang, Chuei-Tang
    Yu, Doug
    [J]. 2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2015,
  • [5] From Fan-out Wafer to Fan-out Panel Level Packaging
    Braun, T.
    Becker, K. -F.
    Raatz, S.
    Bader, V.
    Bauer, J.
    Aschenbrenner, R.
    Voges, S.
    Thomas, T.
    Kahle, R.
    Lang, K. -D.
    [J]. 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), 2015, : 29 - 32
  • [6] High Performance RF Inductors Integrated in Advanced Fan-Out Wafer Level Packaging Technology
    Durand, Cedric
    Gianesello, Frederic
    Pilard, Romain
    Gloria, Daniel
    Imbs, Yvon
    Coffy, Romain
    Marechal, Laurent
    Jin, Yonggang
    Dodo, Yves
    [J]. 2012 IEEE 12TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF), 2012, : 215 - 218
  • [7] Array Antenna Integrated Fan-out Wafer Level Packaging (InFO-WLP) for Millimeter Wave System Applications
    Tsai, Chung-Hao
    Hsieh, Jeng-Shien
    Liu, Monsen
    Yeh, En-Hsiang
    Chen, Hsu-Hsien
    Hsiao, Ching-Wen
    Chen, Chen-Shien
    Liu, Chung-Shi
    Lii, Mirng-Ji
    Wang, Chuei-Tang
    Yu, Doug
    [J]. 2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
  • [8] Foldable Fan-out Wafer Level Packaging
    Braun, T.
    Becker, K. -F.
    Raatz, S.
    Minkus, M.
    Bader, V.
    Bauer, J.
    Aschenbrenner, R.
    Kahle, R.
    Georgi, L.
    Voges, S.
    Woehrmann, M.
    Lang, K. -D.
    [J]. 2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, : 19 - 24
  • [9] InFO_oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet Integration
    Chiang, Y. P.
    Tai, S. P.
    Wu, W. C.
    Yeh, John
    Wang, C. T.
    Yu, Douglas C. H.
    [J]. IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, : 130 - 135
  • [10] A New Integration Technology Platform: Integrated Fan-Out Wafer-Level-Packaging for Mobile Applications
    Yu, Douglas
    [J]. 2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY), 2015,