Design and Implementation of Hybrid Packet Scheduling Schemes with Network Processors

This paper addresses the problem of scheduling variable-size packets from large number of distinct traffic flows. Although the problem of fair packet scheduling in computer networks has received thorough theoretical consideration, practical high-speed packet switching systems remain elementary. The disparity arises because algorithms with theoretically favorable delay and fairness characteristics have unacceptably high computational cost. A variety of hybrid scheduling methods have been proposed as a compromise; this paper discusses the design and implementation of hybrid schedulers. We focus on algorithms suitable for high speed networks, and the study is experimental - the algorithms are implemented on network processor hardware, and actual packet data is used to assess performance.