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- [21] Toward sub-20nm pitch Fin patterning and integration with DSA ADVANCES IN PATTERNING MATERIALS AND PROCESSES XXXIII, 2016, 9779
- [22] Factors that Determine the Optimum Dose for Sub-20nm Resist Systems: DUV, EUV, and e-beam Options ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXIX, 2012, 8325
- [24] Dopant Deactivation: A new challenge in sub-20nm Scaled FinFETs PROCEEDINGS OF TECHNICAL PROGRAM - 2014 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA), 2014,
- [26] Modelling of the Threshold Voltage Distributions of Sub-20nm NAND Flash Memory 2014 IEEE GLOBAL COMMUNICATIONS CONFERENCE (GLOBECOM 2014), 2014, : 2351 - 2356
- [27] Towards high density STT-MRAM at sub-20nm nodes 2018 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA), 2018,
- [28] Methodology for determining CD-SEM measurement condition of sub-20nm resist patterns for 0.33NA EUV lithography METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXIX, 2015, 9424
- [29] Thermal stability and Reliability in SiGe pMOSFETs for sub-20nm DRAM applications 2014 IEEE 6TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2014,
- [30] Novel Flowable CVD Process Technology for sub-20nm Interlayer Dielectrics 2012 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2012,