Design and Simulation of Low Leakage SRAM CELL

In the present study, reverse body biasing and self-controllable-voltage-level (SVL) switch are used to reduce the leakage current in SRAM cell when the circuit is in stand-by mode, resulting in increase in threshold voltage of the transistors. In active mode, threshold voltages of transistors get decreased due to forward body bias which incorporates for high speed memory design. Substrate voltage of PMOS transistors of the cell is switched from VDD to nearly 2(VDD) when circuit is switched from active mode to stand-by mode. In the same manner, the substrate voltage of NMOS transistor is switched from GND to VDD. With the use of SVL switch along with body biasing we could achieve extremely large reduction in leakage current. In the first technique (type-1), supply voltage has been scaled down for better gate leakage reduction as compared to second technique (type-2) where voltage of ground node is increased. In the third technique (type-3), large reduction in leakage current has been attained. The effective voltages across SRAM cell V-VDD=1.23V and VVSS=0.28V are observed. All simulation results have been carried out in Cadence Virtuoso tool in 180 nm technology.