A FPGA based digital predistorter for RF power amplifiers with memory effects

被引：0

作者：

Cesari, Albert ^{[1
]}

Gilabert, Pere L. ^{[2
]}

Bertran, Eduard ^{[2
]}

Montoro, Gabriel ^{[2
]}

Dilhac, Jean M. ^{[1
]}

机构：

[1] CNRS, LAAS, Grp Integrat Syst Gest Energie, Av Colonel Roche 7, F-31077 Toulouse, France

[2] Univ Politecn Cataluna, Dept Signal Theory & Commun, E-08860 Barcelona, Spain

来源：

2007 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE, VOLS 1 AND 2 | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a Field Programmable Gate Array (FPGA) based platform for prototyping digital predistortion (DPD) linearizers, and a scalable DPD architecture is proposed and implemented. This architecture eases the process of meeting transmission linearity requirements, depending of the degree of impairments added by the transmitter chain, and enables a quick migration between different DPD schemes. Details on the internal DPD organization, reconfiguration abilities, as well as experimental results showing DPD linearization of a 10W LDMOS RF power amplifier are provided, giving an insight on actual development scenarios of DPD systems accounting for memory effects.

引用

页码：512 / +

页数：2

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