L3: An FPGA-based multilayer maze routing accelerator

被引：5
|
作者：
Nestor, JA [1 ]
机构：
[1] Lafayette Coll, Dept Elect & Comp Engn, Easton, PA 18042 USA
来源：
MICROPROCESSORS AND MICROSYSTEMS | 2005年 / 29卷 / 2-3期
关键词：
VLSI routine; hardware acceleration; Lee algorithm; FPGA design;
D O I：
10.1016/j.micpro.2004.06.005
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a multi-layer maze routing accelerator which uses a two-dimensional array of processing elements (PEs) implemented in an FPGA. Routing for an L-layer NXN grid is performed by an array of NXN PEs that time-multiplex each layer over the array. This accelerates the classic Lee Algorithm from O(LXd(2)) in software to O(LXd). Each PE can be implemented in 32 look up tables in a Xilinx Virtex-II FPGA, which makes possible routing arrays that are large enough to support detailed routing for VLSI. Cycle measurements show a speedup of 50-75 X over a 2.54 GHz Pentium 4 for a 4-layer 8 X 8 array and 93 X for a 4-layer 16 X 16 array. (C) 2004 Elsevier B.V. All rights reserved.
引用
收藏
页码：87 / 97
页数：11
相关论文
共 50 条
  • [1] L4: An FPGA-based accelerator for detailed maze routing
    Nestor, John A.
    Lavine, JeremY
    2007 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLS 1 AND 2, 2007, : 357 - 362
  • [2] Packet Filtering for FPGA-Based Routing Accelerator
    Antos, David
    Rehak, Vojtech
    Holub, Petr
    CESNET CONFERENCE 2006: FIRST CESNET CONFERENCE ON ADVANCED COMMUNICATIONS AND GRIDS, 2006, : 161 - 173
  • [3] FPGA implementation of a maze routing accelerator
    Nestor, JA
    FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2003, 2778 : 992 - 995
  • [4] An FPGA-Based accelerator for multiphysics modeling
    Huang, XM
    Ma, J
    ERSA '04: THE 2004 INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS, 2004, : 209 - 212
  • [5] FPGA-Based Vehicle Detection and Tracking Accelerator
    Zhai, Jiaqi
    Li, Bin
    Lv, Shunsen
    Zhou, Qinglei
    SENSORS, 2023, 23 (04)
  • [6] An FPGA-based Hardware Accelerator for Iris Segmentation
    Avey, Joe
    Jones, Phillip
    Zambreno, Joseph
    2018 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2018,
  • [7] An FPGA-based Integrated MapReduce Accelerator Platform
    Kachris, Christoforos
    Diamantopoulos, Dionysios
    Sirakoulis, Georgios Ch.
    Soudris, Dimitrios
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2017, 87 (03): : 357 - 369
  • [8] FPGA-Based Programmable Accelerator for Hybrid Processing
    Stefan, Gheorghe M.
    Bira, Calin
    Hobincu, Radu
    Malita, Mihaela
    ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, 2016, 19 (1-2): : 148 - 165
  • [9] An FPGA-Based Accelerator for Frequent Itemset Mining
    Zhang, Yan
    Zhang, Fan
    Jin, Zheming
    Bakos, Jason D.
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2013, 6 (01)
  • [10] FPGA-Based Hardware Accelerator for Matrix Inversion
    Kokkiligadda V.S.K.
    Naikoti V.
    Patkotwar G.S.
    Sabat S.L.
    Peesapati R.
    SN Computer Science, 4 (2)
12345