High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz

被引：59
|
作者：
Singh, U [1 ]
Green, MM [1 ]
机构：
[1] Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2005年 / 40卷 / 08期
基金：
美国国家科学基金会;
关键词：
broadband communication; CMOS analog integrated circuits; CMOS integrated circuits; frequency conversion; high-speed integrated circuits;
D O I：
10.1109/JSSC.2005.852420
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations of these circuits in a 0.13-mu m CMOS process show a significant improvement in high-frequency operation compared to a conventional D flip-flop-based divider. Measured sensitivity curves of these dividers give maximum frequency of operation ranging from 20 to 38 GHz with power consumption of 12 mW from a 1.8-V supply voltage.
引用
收藏
页码：1658 / 1661
页数：4
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