A Rigorous Approach to the Robust Design of Continuous-Time ΣΔ Modulators

被引:11
|
作者
De Vuyst, Bart [1 ]
Rombouts, Pieter [1 ]
Gielen, Georges [2 ]
机构
[1] Univ Ghent, Elect & Informat Syst ELIS, B-9000 Ghent, Belgium
[2] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Louvain, Belgium
关键词
Analog-to-digital (A/D) conversion; continuous-time sigma-delta (Sigma Delta) modulation; robust performance; robust stability; EXCESS-LOOP-DELAY; SIGNAL BANDWIDTH; DYNAMIC-RANGE; CLOCK JITTER; COMPENSATION; OPTIMIZATION; CONVERTERS; QUANTIZER; CMOS; ADC;
D O I
10.1109/TCSI.2011.2158702
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper we present a framework for robust design of continuous-time Sigma Delta modulators. The approach allows to find a modulator which maintains its performance ( stability, guaranteed peak SNR, ...) over all the foreseen parasitic effects, provided it exists. For this purpose, we have introduced the S-figure as a criterion for the robustness of a continuous-time Sigma Delta modulator. This figure, inspired by the worst-case-distance methodology, indicates how close a design is to violating one of its performance requirements. Optimal robustness is obtained by optimizing this S-figure. The approach is illustrated through various design examples and is able to find modulators that are robust to excess loop delay, clock jitter and coefficient variations. As an application of the approach, we have quantified the effect of coefficient trimming. Even with poor trim resolution, good performance can be achieved provided beneficial initial system parameters are chosen. Another example illustrates the fact that also the out-of-band peaking behavior of the signal transfer function can be controlled with our design framework.
引用
收藏
页码:2829 / 2837
页数:9
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