Simulation and Experimentation of 57-Level Inverter

被引：0

作者：

Vijayaraja, L. ^{[1
]}

Nandhinipriya, V ^{[2
]}

Dhanasekar, R. ^{[1
]}

Kumar, S. Ganesh ^{[2
]}

Rivera, M. ^{[3
]}

机构：

[1] Sri Sairam Inst Technol, Elect & Elect Engn Dept, Chennai, Tamil Nadu, India

[2] Anna Univ, Elect & Elect Engn Dept, CEG Campus, Chennai, Tamil Nadu, India

[3] Univ Talca, Fac Engn, Ctr Tecnol Convers Energia, Dept Elect Engn, Campus Curico, Maule, Chile

来源：

2021 IEEE IFAC INTERNATIONAL CONFERENCE ON AUTOMATION/XXIV CONGRESS OF THE CHILEAN ASSOCIATION OF AUTOMATIC CONTROL (IEEE IFAC ICA - ACCA2021) | 2021年

关键词：

Harmonic analysis; Inverters; Multilevel systems; Pulse width modulation; Power semiconductor devices;

D O I：

10.1109/ICAACCA51523.2021.9465284

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a 57-level asymmetric multilevel inverter is proposed with less number of devices and sources. Working process of symmetric and asymmetric structures are studied and tested using MATLAB. Proposed asymmetric structure is compared and analyzed against other multilevel inverter topologies. Resistive load and reactive load is considered for symmetric and asymmetric inverter simulation. Further, symmetric and asymmetric configurations are compared in terms of harmonic content. Proto-type development is carried out for the fifty-seven-level asymmetric inverter and the test results are presented. From the results, it is concluded that both symmetric and asymmetric structure yield low harmonic output waveforms.

引用

页数：8

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