Influence of gate length on ESD-performance for deep submicron CMOS technology

被引：3
|
作者：
Bock, K
Keppens, B
De Heyn, V
Groeseneken, G
Ching, LY
Naem, A
机构：
[1] IMEC, B-3001 Louvain, Belgium
[2] Natl Semicond Corp, Santa Clara, CA 95052 USA
来源：
MICROELECTRONICS RELIABILITY | 2001年 / 41卷 / 03期
关键词：
Bipolar integrated circuits - Electric discharges - Electrostatics - Gates (transistor) - Integrated circuit testing - MOSFET devices;
D O I：
10.1016/S0026-2714(00)00243-2
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
ESD-performance of grounded-gate nMOS protection structures has been observed for a standard 0.25 mum CMOS epitaxial layer based technology. The shortest gate lengths show unexpectedly lower ESD-thresholds, leading to an optimum performance for longer gate length devices attributed to the trade off between power dissipation and melt volume of the parasitic bipolar. (C) 2001 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：375 / 383
页数：9
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