A novel asynchronous control unit and the application to a pipelined multiplier

被引：0

作者：

Chiang, JS ^{[1
]}

Liao, JY ^{[1
]}

机构：

[1] Tamkang Univ, Dept Elect Engn, Taipei, Taiwan

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper is to discuss the technique for asynchronous circuit design by using a novel asynchronous control unit. We use the very commonly used device, pass-transistor multiplexer, to design and implement the asynchronous control unit. Even though the architecture of the control unit is simple, the efficiency is well. A multiplier with pipelined structure has been designed to verify the usefulness of this technique. We use TSMC's 0.6um SPDM process to design and implement an 8-b x 8-b pipelined multiplier. The HSPICE simulation shows that the feed through rate of the inputs can be as high as 250MHz.

引用

页码：A169 / A172

页数：4

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