Low-voltage power-efficient BiDPL adder for VLSI applications

This paper presents a new low-voltage power-efficient adder design, based on a Bipolar Double Pass-Transistor Logic (BiDPL), suitable for VLSI applications. The new adder delivers significantly higher performance for the same amount of power needed to execute an adder operation. The new BiDPL adder is more power-efficient at very low supply voltages (1.1-2 V) than a conventional CMOS adder design and the best low-voltage low-power adder reported in Literature. The proposed BiDPL adder outperforms in power-efficiency both designs by as much as 61% and 535% respectively. Under optimal conditions (V-dd = 1.6 V), the BiDPL adder is 40% more efficient than a standard CMOS adder and up to 300% more efficient than the low-power adder proposed by Wu and Ng (Electronics Letters, Vol. 33, No. 8, 1997). At 1.2 V power supply, the proposed new BiDPL adder is 46% more power-efficient than a standard CMOS adder. The low-power low-voltage adder proposed by Wu and Ng is not operational below 1.5 V. All experimental circuits were designed and fabricated with 0.8 mu m BiCMOS technology. (C) 1999 Elsevier Science Ltd. All rights reserved.