Slew-aware Fast Clock Tree Synthesis with Buffer Sizing

被引：0

作者：

Choi, Mujun ^{[1
]}

Oh, Deokkeun ^{[1
]}

Kim, Juho ^{[1
]}

机构：

[1] Sogang Univ, Dept Comp Sci & Engn, Seoul, South Korea

来源：

2018 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC) | 2018年

关键词：

skew; slew; buffer sizing; DME; Fast CTS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Clock tree synthesis (CTS) is a critical part on the total performance of chip. Buffer insertion is required in clock tree to prevent signal degradation and satisfy slew constraints. Also, buffer sizing minimizes power and skew in clock tree network. In this paper, we proposed slew-aware fast buffer insertion/sizing methodology in CTS based on DME to meet the skew constraints. The experiment results show the proposed sizing method reduce about 13.47% power consumption and 49.03% runtime compared to LP-based method.

引用

页码：271 / 274

页数：4

共 50 条

[11] Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs
Zhao, Xin
Lim, Sung Kyu
2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 172 - 177
[12] Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, United States
Proc Asia South Pac Des Autom Conf, 1600, (175-180):
[13] Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
Wang, Chun-Kai
Chang, Yeh-Chi
Chen, Hung-Ming
Chin, Ching-Yu
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2014, 20 (01) : 1 - 23
[14] Fast clock scheduling and an application to clock tree synthesis
Ewetz, Rickard
Koh, Cheng-Kok
INTEGRATION-THE VLSI JOURNAL, 2017, 56 : 115 - 127
[15] X-architecture Clock Tree Construction Associated with Buffer Insertion and Sizing
Tsai, Chia-Chun
Kuo, Chung-Chieh
Lee, Trong-Yen
Wu, Jan-Ou
2009 1ST ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2009, : 298 - +
[16] Lightweight Buffer Insertion for Clock Tree Synthesis Visualization
Kwon, Nayoung
Park, Daejin
2022 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC), 2022,
[17] Clock Tree Synthesis under Aggressive Buffer Insertion
Chen, Ying-Yu
Dong, Chen
Chen, Deming
PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 86 - 89
[18] Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem
Rakai, Logan
Farshidi, Amin
Westwick, David
Behjat, Laleh
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2014, 33 (04) : 532 - 545
[19] Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis
Figueiredo, Monica
Aguiar, Rui L.
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2010, 5953 : 46 - +
[20] Buffer Sizing for Near-Threshold Clock Tree using Improved Genetic Algorithm
Sun, Yiran
Zhou, Ju
Zhang, Shiying
Wang, Xuexiang
2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,

← 1 2 3 4 5 →